Oscillators are a key component in the design of radio frequency (RF) communication systems. The estimation and calibration of the modulation gain of an RF oscillator is currently an area of active research. Accurate knowledge of this gain significantly reduces the complexity and increases the performance of the transmit frequency modulation path. It is particularly beneficial in systems implemented in deep submicron CMOS and based on orthogonal frequency/phase and amplitude (i.e. polar) topology. Estimation of RF oscillator frequency-modulation gain is especially important in low-cost high-volume transceivers. In such systems, the phase locked loop sets the loop bandwidth while the transmitter sets the transfer function of the direct frequency modulation path wherein the acceptable gain estimation error ranges from less than 1% for CDMA to several percents for GSM and Bluetooth, for example.
A well-known method for achieving indirect frequency/phase modulation is the use of sigma-delta modulation of the feedback division ratio in a fractional-N PLL frequency synthesizer, described in T. Riley et al., “A simplified continuous time modulation technique,” IEEE Trans. on Circuits and Systems II, Vol. 41, no. 5, pp. 321-328, May 1994.
To compensate high-frequency attenuation in a PLL with limited bandwidth, a prior art technique to boost high-frequency components in the digital modulating signal is described in M. H. Perrott et al., “A 27-mW CMOS fractional-N synthesizer using digital compensation for 2.5 Mb/s GFSK modulation,” IEEE J. Solid-State Circuits, vol. 32, no. 12, pp. 2048-2060, December, 1997. Unfortunately, the PLL frequency response is subject to process, voltage and temperature (PVT) variations of the charge pump, loop filter and voltage controlled oscillator (VCO). To match the precompensation filter to the inverse frequency response of the PLL, a prior art automatic online calibration technique is described in D. R. McMahill et al., “A 2.5 Mb/s GFSK 5.0 Mb/s 4-FSK automatically calibrated Σ-Δ frequency synthesizer,” IEEE J. Solid-State Circuits, vol. 37, no. 1, pp. 18-26, January, 2002. This technique is adapted to measure the phase error between the demodulated RF output and the reference input and adjust the PLL loop gain via the charge pump current. A disadvantage of this technique, however, is the cost of additional circuitry amounting to approximately ⅓ of the PLL, including a reference error filter, DPLL, vector test and RF phase quantizer. Further, this technique suffers from a slow time constant of 200 ms. Another prior art calibration technique that measures the PLL loop magnitude response to a training tone whose frequency is located slightly beyond the loop bandwidth is described in S. T. Lee et al., “A quad-band GSM-GPRS transmitter with digital auto-calibration,” IEEE J. Solid State Circuits, vol. 39, no. 12, pp. 2200-2214, December, 2004.
A two-point direct modulation scheme is described in M. Bopp et al., “A DECT transceiver chip set using SiGe technology,” Proc. of IEEE Solid-State Circuits Conf., pp. 68-69, 447, February 1999. This modulation scheme directly controls the oscillator frequency while compensating for the resulting loop reaction. A disadvantage of this approach, however, is that it is mostly analog in nature and requires precise calibration of the oscillator and other PLL analog components. A fully-digital approach is described in R. B. Staszewski et al., “Just-in-time gain estimation of an RF digitally-controlled oscillator for digital direct frequency modulation,” IEEE Trans. on Circuits and, Systems II, vol. 50, no. 11, pp. 887-892, November 2003. This fully digital technique only requires calibration of the oscillator. The calibration digitally estimates the oscillator modulation gain before each packet by forcing an exact frequency step and digitally measuring the dc loop response as described in R. B. Staszewski et al., “Just-in-time gain estimation of an RF digitally-controlled oscillator,” Proc. of 2003 IEEE Custom Integrated Circuits Conf., pp. 571-574, September 2003.
The prior art techniques discussed hereinabove suffer from disadvantages such as they (1) require a dedicated time for background calibration, which makes them suitable only for packetized operations, such as GSM/EDGE, but not WCDMA, (2) require dedicated and expensive hardware, (3) are dc based and are thus sensitive to frequency drift of the oscillator, or (4) require factory calibration. There is thus a need for a gain calibration technique that consumes little additional hardware, is very accurate, can continuously track changes in the gain with temperature and/or supply voltage and can adapt using either the training sequence or user data. Further it is desirable that the gain calibration technique be suitable for use in UMTS (i.e. GSM/EDGE and WCDMA) applications. In the case of non-constant envelope signaling, the gain calibration technique should be applicable to the frequency/phase portion of a polar modulation transmitter.